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19-3164; Rev 1; 5/04
KIT ATION EVALU ABLE AVAIL
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Features
3s (max) 12-Bit Settling Time to 0.5 LSB Quad, 12-/10-/8-Bit Serial DACs in TSSOP and Thin QFN (5mm x 5mm x 0.8mm) Packages 1 LSB (max) INL and DNL at 12-Bit Resolution Two User-Programmable Digital I/O Ports Single +2.7V to +5.25V Analog Supply +1.8V to AVDD Digital Supply 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSPCompatible Serial Interface Glitch-Free Outputs Power Up to Zero Scale, Midscale, or Full Scale Controlled by PU Pin Unity-Gain or Force-Sense-Configured Output Buffers
General Description
The MAX5580-MAX5585 quad, 12-/10-/8-bit, voltageoutput, digital-to-analog converters (DACs) offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a +2.7V to +5.25V analog supply and a separate +1.8V to +5.25V digital supply. The 20MHz, 3-wire, serial interface is compatible with SPITM, QSPITM, MICROWIRETM, and digital signal processor (DSP) protocol applications. Multiple devices can share a common serial interface in directaccess or daisy-chained configuration. The MAX5580- MAX5585 provide two multifunctional, user-programmable, digital I/O ports. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Software-selectable FAST and SLOW settling modes decrease settling time in FAST mode, or reduce supply current in SLOW mode. The MAX5580/MAX5581 are 12-bit DACs, the MAX5582/MAX5583 are 10-bit DACs, and the MAX5584/MAX5585 are 8-bit DACs. The MAX5580/ MAX5582/MAX5584 provide unity-gain-configured output buffers, while the MAX5581/MAX5583/MAX5585 provide force-sense-configured output buffers. The MAX5580-MAX5585 operate over the extended -40C to +85C temperature range and are available in space-saving, 5mm x 5mm x 0.8mm, 20-pin, thin QFN and TSSOP packages.
MAX5580-MAX5585
Ordering Information
PART MAX5580AEUP* MAX5580AETP* TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP-EP** 20 Thin QFN-EP**
*Future product--contact factory for availability. Specifications are preliminary. **EP = Exposed paddle. Ordering Information continued at end of data sheet.
Applications
Portable Instrumentation Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Automatic Tuning Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Controls Motion Control Microprocessor (P)-Controlled Systems Power Amplifier Control Fast Parallel-DAC to Serial-DAC Upgrades
PART MAX5580AEUP MAX5580AETP MAX5580BEUP MAX5580BETP MAX5581AEUP MAX5581AETP MAX5581BEUP MAX5581BETP MAX5582EUP MAX5582ETP MAX5583EUP MAX5583ETP MAX5584EUP MAX5584ETP MAX5585EUP MAX5585ETP
Selector Guide
OUTPUT BUFFER CONFIGURATION Unity gain Unity gain Unity gain Unity gain Force sense Force sense Force sense Force sense Unity gain Unity gain Force sense Force sense Unity gain Unity gain Force sense Force sense RESOLUTION (BITS) 12 12 12 12 12 12 12 12 10 10 10 10 8 8 8 8 INL (LSB max) 1 1 4 4 1 1 4 4 1 1 1 1 0.5 0.5 0.5 0.5
Pin Configurations appear at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
ABSOLUTE MAXIMUM RATINGS
AVDD to DVDD ........................................................................6V AGND to DGND ..................................................................0.3V AVDD to AGND, DGND.............................................-0.3V to +6V DVDD to AGND, DGND ............................................-0.3V to +6V FB_, OUT_, REF to AGND ........-0.3V to the lower of (AVDD + 0.3V) or +6V SCLK, DIN, CS, PU, DSP to DGND .......-0.3V to the lower of (DVDD + 0.3V) or +6V UPIO1, UPIO2 to DGND ...............-0.3V to the lower of (DVDD + 0.3V) or +6V Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 21.7mW/C above +70C)........1739mW 20-Pin Thin QFN (derate 20.8mW/C above +70C) ....1667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER STATIC ACCURACY MAX5580/MAX5581 Resolution N MAX5582/MAX5583 MAX5584/MAX5585 VREF = 2.5V at AVDD = 2.7V and VREF = 4.096V at AVDD = 5.25V (Note 2) MAX5580A/MAX5581A (12 bit) MAX5580B/MAX5581B (12 bit) MAX5582/MAX5583 (10 bit) MAX5584/MAX5585 (8 bit) 2 0.5 0.125 12 10 8 1 4 LSB 1 0.5 1 5 5 5 5 5 MAX5580A/MAX5581A (12 bit) Gain Error GE Full-scale output MAX5580B/MAX5580B (12 bit) MAX5582/MAX5583 (10 bit) MAX5584/MAX5585 (8 bit) Gain-Error Drift 20 5 2 1 4 40 10 3 ppm of FS/C LSB 25 25 25 ppm of FS/C mV LSB Bits SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Guaranteed monotonic (Note 2) MAX5580A/MAX5581A (12 bit), decimal code = 40 MAX5580B/MAX5581B (12 bit), decimal code = 40 MAX5582/MAX5583 (10 bit), decimal code = 20 MAX5584/MAX5585 (8 bit), decimal code = 5
Offset Error
VOS
Offset-Error Drift
2
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Power-Supply Rejection Ratio REFERENCE INPUT Reference-Input Range Reference-Input Resistance Reference Leakage Current DAC OUTPUT CHARACTERISTICS SLOW mode, full scale Output-Voltage Noise FAST mode, full scale Output-Voltage Range (Note 3) DC Output Impedance Short-Circuit Current Power-Up Time Wake-Up Time Output OUT_ and FB_ Open-Circuit Leakage Current DIGITAL OUTPUTS (UPIO_) Output High Voltage Output Low Voltage VOH VOL ISOURCE = 0.5mA ISINK = 2mA DVDD 2.7V Input High Voltage VIH DVDD < 2.7V DVDD > 3.6V Input Low Voltage Input Leakage Current Input Capacitance VIL IIN CIN 2.7V DVDD 3.6V DVDD < 2.7V 0.1 10 2.4 0.7 x DVDD 0.8 0.6 0.2 1 A pF V V DVDD 0.5 0.4 V V AVDD = 5V, OUT_ to AGND, full scale, FAST mode AVDD = 3V, OUT_ to AGND, full scale, FAST mode From DVDD, applied until interface is functional Coming out of shutdown, outputs settled Programmed in shutdown mode, force-sense outputs only Unity-gain output Force-sense output Unity gain Force sense Unity gain Force sense 0 0 38 57 45 30 40 0.01 60 85 67 140 110 AVDD AVDD / 2 V mA s s A VRMS VREF RREF Normal operation (no code dependence) Shutdown mode 0.25 145 200 0.5 1 AVDD V k A SYMBOL PSRR CONDITIONS Full-scale output, AVDD = 2.7V to 5.25V MIN TYP 200 MAX UNITS V/V
MAX5580-MAX5585
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER PU INPUT Input High Voltage Input Low Voltage Input Leakage Current DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR FAST mode SLOW mode MAX5580/MAX5581 from code 322 to code 4095 to 0.5 LSB FAST mode MAX5582/MAX5583 from code 10 to code 1023 to 0.5 LSB MAX5584/MAX5585 from code 3 to code 255 to 0.5 LSB tS MAX5580/MAX5581 from code 322 to code 4095 to 0.5 LSB SLOW mode MAX5582/MAX5583 from code 10 to code 1023 0.5 LSB MAX5584/MAX5585 from code 3 to code 255 to 0.5 LSB FB_ Input Voltage FB_ Input Current Reference -3dB Bandwidth (Note 5) Digital Feedthrough Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Unity gain Force sense CS = DVDD, code = zero scale, any digital input from 0 to DVDD and DVDD to 0, f = 100kHz Major carry transition (Note 6) 200 150 0.1 2 15 0 3.6 1.6 2 1.5 1 3 2.5 2 3 3 2 s 6 6 4 VREF / 2 0.1 V A kHz nV-s nV-s nV-s V/s VIH-PU VIL-PU IIN-PU PU still considered floating when connected to a tri-state bus DVDD 200mV 200 200 V mV nA SYMBOL CONDITIONS MIN TYP MAX UNITS
Voltage-Output Settling Time (Note 4), Figure 5
4
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.25V, DVDD = 1.8V to AVDD, AGND = 0, DGND = 0, VREF = 2.5V (for AVDD = 2.7V to 5.25V), VREF = 4.096V (for AVDD = 4.5V to 5.25V), RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Digital Supply Voltage Range AVDD DVDD SLOW mode, all digital inputs Unity gain at DGND or DVDD, no load, Force sense VREF = 4.096V FAST mode, all digital inputs at DGND or DVDD, no load, VREF = 4.096V Unity gain Force sense 2.70 1.8 0.9 1.6 1.6 2.3 5.25 AVDD 1.6 2.4 mA 4 4 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5580-MAX5585
Operating Supply Current
IAVDD + IDVDD
Shutdown Supply Current
IAVDD(SHDN) No clocks, all digital inputs at DGND or DVDD, all + DACs in shutdown mode IDVDD(SHDN)
0.5
1
A
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_, and VOUT (max) = VREF / 2, unless otherwise noted. Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code 1023 for the MAX5582/MAX5583 (10 bit), and code 5 to code 255 for the MAX5584/MAX5585 (8 bit). Note 3: Represents the functional range. The linearity is guaranteed at VREF = 2.5V (for AVDD from 2.7V to 5.25V), and VREF = 4.096V (for AVDD = 4.5V to 5.25V). See the Typical Operating Characteristics section for linearity at other voltages. Note 4: Guaranteed by design. Note 5: The reference -3dB bandwidth is measured with a 0.1VP-P sine wave on VREF and with full-scale input code. Note 6: DC crosstalk is measured as follows: outputs of DACA-DACD are set to full scale and the output of DACD is measured. While keeping DACD unchanged, the outputs of DACA-DACC are transitioned to zero scale and the VOUT of DACD is measured.
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
TIMING CHARACTERISTICS--DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup Time DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 20 100 20 100 100 100 ns SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 10 45 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 5 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20 20
ns ns ns ns ns ns ns
6
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SCLK Rise to CS Fall Setup TIme DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Rise to DOUTDC1 Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Rise Hold Time CS Pulse-Width High UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Rise LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th rising edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 40 200 40 200 200 200 ns SYMBOL fSCLK tCH tCL tCSS tCSH tCS0 tDS tDH tDO1 tDO2 tCS1 tCSW CL = 20pF, UPIO_ = DOUTDC1 mode CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB mode MICROWIRE and SPI modes 0 and 3 20 90 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 2.7V 40 40 20 5 10 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
MAX5580-MAX5585
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40 40
ns ns ns ns ns ns ns
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7
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
TIMING CHARACTERISTICS--DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 20 100 20 100 100 100 ns SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 10 45 20 20 (Note 7) (Note 7) CONDITIONS 2.7V < DVDD < 5.25V 20 20 10 10 5 10 10 12 5 30 30 MIN TYP MAX 20 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
20 20
ns ns ns ns ns ns ns
8
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS--DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup Time DSP Fall to SCLK Fall Setup Time SCLK Fall to CS Rise Hold Time SCLK Fall to CS Fall Delay SCLK Fall to DSP Fall Delay DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Rise to DOUT_ Valid Propagation Delay SCLK Fall to DOUT_ Valid Propagation Delay CS Rise to SCLK Fall Hold Time CS Pulse-Width High DSP Pulse-Width High DSP Pulse-Width Low UPIO_ TIMING CHARACTERISTICS DOUT Tri-State Time when Exiting DOUTDC0, DOUTDC1, and UPIO Modes DOUTRB Tri-State Time from CS Rise DOUTRB Tri-State Enable Time from 8th SCLK Fall LDAC Pulse-Width Low LDAC Effective Delay CLR, MID, SET Pulse-Width Low GPO Output Settling Time GPO Output High-Impedance Time tDOZ CL = 20pF, from end of write cycle to UPIO_ in high impedance CL = 20pF, from rising edge of CS to UPIO_ in high impedance CL = 20pF, from 8th falling edge of SCLK to UPIO_ driven out of tri-state Figure 5 Figure 6 Figure 5 Figure 6 40 200 40 200 200 200 ns SYMBOL fSCLK tCH tCL tCSS tDSS tCSH tCS0 tDS0 tDS tDH tDO1 tDO2 tCS1 tCSW tDSW tDSPWL (Note 8) CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB mode CL = 20pF, UPIO_ = DOUTDC0 mode MICROWIRE and SPI modes 0 and 3 20 90 40 40 (Note 7) (Note 7) CONDITIONS 1.8V < DVDD < 2.7V 40 40 20 20 5 10 15 20 5 60 60 MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX5580-MAX5585
tDRBZ tZEN tLDL tLDS tCMS tGP tGPZ
40 40
ns ns ns ns ns ns ns
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the following edge. In the case of a 0.5 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns (2.7V) or 50ns (1.8V). Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of operation.
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9
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Typical Operating Characteristics
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12 BIT)
MAX5580-85 toc01
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (10 BIT)
MAX5580-85 toc02
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8 BIT)
MAX5580-85 toc03
4 3 2 1 INL (LSB)
1.00 0.75 0.50 0.25 INL (LSB) 0 -0.25 -0.50 -0.75
0.50
0.25 INL (LSB)
0 -1 -2 -3 B GRADE -4 0 1024 2048 3072 DIGITAL INPUT CODE 4095
0
-0.25
-1.00 0 256 512 768 DIGITAL INPUT CODE 1023
-0.50 0 64 128 192 DIGITAL INPUT CODE 255
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (12 BIT)
MAX5580-85 toc04
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10 BIT)
MAX5580-85 toc05
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (8 BIT)
MAX5580-85 toc06
0.50
0.2
0.050
0.25 DNL (LSB)
0.1 DNL (LSB)
0.025 DNL (LSB)
0
0
0
-0.25
-0.1
-0.025
B GRADE -0.50 0 1024 2048 3072 DIGITAL INPUT CODE 4095 -0.2 0 256 512 768 DIGITAL INPUT CODE 1023 -0.050 0 64 128 192 DIGITAL INPUT CODE 255
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE (12 BIT)
MAX5580-85 toc07
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE (12 BIT)
0.4 0.3 0.2 DNL (LSB) INL (LSB) 0.1 0 -0.1 -0.2 -0.3
MAX5580-85 toc08
INTEGRAL NONLINEARITY vs. TEMPERATURE (12 BIT)
3 2 1 0 -1 -2
MAX5580-85 toc09
4 3 2 1 INL (LSB) 0 -1 -2 -3 -4 1.0 1.5 2.0 2.5 3.0 3.5 VREF (V) 4.0 4.5 B GRADE MIDSCALE
0.5
4
-0.4 -0.5 5.0 1.0 1.5 2.0 2.5 3.0 VREF (V) 3.5
B GRADE MIDSCALE 4.0 4.5 5.0
-3 -4
B GRADE MIDSCALE -40 -15 10 35 60 85
TEMPERATURE (C)
10
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12 BIT)
MAX5580-85 toc10
MAX5580-MAX5585
SUPPLY CURRENT vs. DIGITAL INPUT CODE (FORCE SENSE)
MAX5580-85 toc11
SUPPLY CURRENT vs. DIGITAL INPUT CODE (UNITY GAIN)
MAX5580-85 toc12
0.2
2.0
1.0
SUPPLY CURRENT (mA)
0
1.0
SUPPLY CURRENT (mA) SLOW MODE 12 BIT NO LOAD
0.1 DNL (LSB)
1.5
0.75
0.50
-0.1 B GRADE MIDSCALE -0.2 -40 -15 10 35 60 85 TEMPERATURE (C)
0.5
0.25 SLOW MODE 12 BIT NO LOAD 0
0 0 1024 2048 3072 DIGITAL INPUT CODE 4095
0
1024 2048 3072 DIGITAL INPUT CODE
4095
SUPPLY CURRENT vs. SUPPLY VOLTAGE (FORCE SENSE)
2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
MAX5580-85 toc13
SUPPLY CURRENT vs. SUPPLY VOLTAGE (UNITY GAIN)
MAX5580-85 toc14
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
95 90 85 80 75 70 65 60 55 50 AVDD = DVDD NO LOAD I = IAVDD + IDVDD 2.70 3.40 4.10 4.80 5.25 FORCE SENSE UNITY GAIN
MAX5580-85 toc15
1.6 1.4 SUPPLY CURRENT (mA) 1.2 SLOW MODE 1.0 0.8 0.6 0.4 0.2 0 I = IAVDD + IDVDD AVDD = DVDD NO LOAD 2.70 3.40 4.10 4.80 FAST MODE
100 SHUTDOWN SUPPLY CURRENT (nA)
FAST MODE
SUPPLY CURRENT (mA)
SLOW MODE
I = IAVDD + IDVDD AVDD = DVDD NO LOAD 2.70 3.40 4.10 4.80 5.25
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OFFSET ERROR vs. TEMPERATURE
MAX5580-85 toc16
GAIN ERROR vs. TEMPERATURE
MAX5580-85 toc17
OUTPUT VOLTAGE vs. OUTPUT SOURCE/SINK CURRENT
MIDSCALE 2.0 OUTPUT VOLTAGE (V)
MAX5580-85 toc18
7 6 OFFSET ERROR (LSB) 5 4 3 2 1 0
CODE = 40 UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV B GRADE
0 -1 -2 GAIN ERROR (LSB) -3 -4 -5 -6 -7 -8 UNITY GAIN B GRADE UNITY GAIN: 1 LSB = 1mV FORCE SENSE: 1 LSB = 0.5mV -40 -15 10 35 60 FORCE SENSE
2.5
1.5
FORCE SENSE
1.0
0.5 UNITY GAIN VREF = 4.096V -15 -10 -5 0 IOUT (mA) 5 10 15
UNITY GAIN -40 -15 10 35 60 85
-9 -10
0 85
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
11
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Typical Operating Characteristics (continued)
(AVDD = DVDD = 5V, VREF = 4.096V, RL = 10k, CL = 100pF, speed mode = FAST, PU = floating, TA = +25C, unless otherwise noted.)
MAJOR-CARRY TRANSITION GLITCH
MAX5580-85 toc19
SETTLING TIME POSITIVE
MAX5580-85 toc20
SETTLING TIME NEGATIVE
MAX5580-85 toc21
FULL-SCALE TRANSITION
FULL-SCALE TRANSITION
CS 2V/div
CS 2V/div
CS 2V/div
(AC COUPLED) OUT_ 10mV/div 200ns/div 400ns/div
OUT_ 2V/div
OUT_ 2V/div
400ns/div
REFERENCE INPUT BANDWIDTH
MAX5580-85 toc22
REFERENCE FEEDTHROUGH AT 1kHz
-22 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -142
MAX5580-85 toc23
DAC-TO-DAC CROSSTALK
MAX5580-85 toc24
5 0 -5 GAIN (dB) -10 -15 -20 -25 1 VREF = 0.1VP-P AT 4.096VDC UNITY GAIN 10 100 FREQUENCY (Hz) 1k
OUTA-OUTC 2V/div
OUTD 2mV/div
10k
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz)
200s/div
DIGITAL FEEDTHROUGH
MAX5580-85 toc25
POWER-UP GLITCH
MAX5580-85 toc26
EXITING SHUTDOWN TO MIDSCALE
MAX5580-85 toc27
SCLK 2V/div AVDD 2V/div UPIO_ 2V/div
OUT_ (AC-COUPLED) 5mV/div PU = DVDD 1s/div 20s/div
OUT_ 2V/div PU = FLOAT 10s/div
OUT_ 2V/div
12
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Pin Description
PIN MAX5580 MAX5582 MAX5584 TSSOP 1 2 3, 5, 17, 19 -- 4 -- 6 THIN QFN 19 20 1, 3, 15, 17 -- 2 -- 4 MAX5581 MAX5583 MAX5585 TSSOP 1 2 -- 3 4 5 6 THIN QFN 19 20 -- 1 2 3 4 AGND AVDD N.C. FBB OUTB FBA OUTA Analog Ground Analog Supply No Connection. Not internally connected. Feedback for DACB DACB Output Feedback for DACA DACA Output Power-Up State Select Input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to DGND to set OUT_ to zero scale upon power-up. Float PU to set OUT_ to midscale upon power-up. Active-Low Chip-Select Input Serial Clock Input Serial Data Input User-Programmable Input/Output 1 User-Programmable Input/Output 2 Digital Supply Digital Ground Clock Enable. Connect DSP to DVDD to clock in data on the rising edge of SCLK. Connect DSP to DGND to clock in data on the falling edge of SCLK. DACD Output Feedback for DACD DACC Output Feedback for DACC Reference Input Exposed Pad. Connect to AGND. NAME FUNCTION
MAX5580-MAX5585
7
5
7
5
PU
8 9 10 11 12 13 14 15 16 -- 18 -- 20 EP
6 7 8 9 10 11 12 13 14 -- 16 -- 18 EP
8 9 10 11 12 13 14 15 16 17 18 19 20 EP
6 7 8 9 10 11 12 13 14 15 16 17 18 EP
CS SCLK DIN UPIO1 UPIO2 DVDD DGND DSP OUTD FBD OUTC FBC REF Exposed Pad
______________________________________________________________________________________
13
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Functional Diagrams
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
MAX5580 MAX5582 MAX5584
DSP
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER
PU
DECODE CONTROL INPUT REGISTER A DAC REGISTER A DACA
OUTA
OUTD INPUT REGISTER D DAC REGISTER D DACD
REF
14
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Functional Diagrams (continued)
MAX5580-MAX5585
AVDD
DVDD
AGND
DGND
CS SCLK DIN
SERIAL INTERFACE CONTROL
DSP
MAX5581 MAX5583 MAX5585
16-BIT SHIFT REGISTER MUX DOUT REGISTER
UPIO1 UPIO2
UPIO1 AND UPIO2 LOGIC
POWER-DOWN LOGIC AND REGISTER
FBA
PU
DECODE CONTROL INPUT REGISTER A DAC REGISTER A DACA
OUTA
FBD
OUTD INPUT REGISTER D DAC REGISTER D DACD
REF
______________________________________________________________________________________
15
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Detailed Description
The MAX5580-MAX5585 quad, 12-/10-/8-bit, voltageoutput DACs offer buffered outputs and a 3s maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and a separate 1.8V to AVDD digital supply. The MAX5580-MAX5585 include an input register and DAC register for each channel and a 16-bit data-in/data-out shift register. The 3-wire serial interface is compatible with SPI, QSPI, MICROWIRE, and DSP applications. The MAX5580-MAX5585 provide two user-programmable digital I/O ports, which are programmed through the serial interface. The externally selectable power-up states of the DAC outputs are either zero scale, midscale, or full scale. Use the serial interface to set the shutdown output impedance of the amplifiers to 1k or 100k for the MAX5580/MAX5582/MAX5584 and 1k or high impedance for the MAX5581/MAX5583/MAX5585. The DAC outputs can drive a 10k (typ) load and are stable with up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale, midscale, or zero scale, depending on the configuration of the PU input. Connect PU to DVDD to set OUT_ to full scale upon power-up. Connect PU to digital ground (DGND) at power-up to set OUT_ to zero scale. Leave PU floating to set OUT_ to midscale.
Reference Input
The reference input, REF, accepts both AC and DC values with a voltage range extending from analog ground (AGND) to AVDD. The voltage at REF sets the full-scale output of the DACs. Determine the output voltage using the following equations: Unity-gain versions: VOUT_ = (VREF x CODE) / 2N Force-sense versions (FB_ connected to OUT_): VOUT = 0.5 x (VREF x CODE) / 2N where CODE is the numeric value of the DAC's binary input code and N is the bits of resolution. For the MAX5580/MAX5581, N = 12 and CODE ranges from 0 to 4095. For the MAX5582/MAX5583, N = 10 and CODE ranges from 0 to 1023. For the MAX5584/ MAX5585, N = 8 and CODE ranges from 0 to 255. Use the minature MAX6126 low-dropout, ultra-low-noise reference for optimum performance.
Digital Interface
The MAX5580-MAX5585 use a 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP protocol applications (Figures 1 and 2). Connect DSP to DVDD before power-up to clock data in on the rising edge of SCLK. Connect DSP to DGND before power-up to clock data in on the falling edge of SCLK. After powerup, the device enters DSP frame-sync mode on the first rising edge of DSP. Refer to the MAX5580-MAX5585 Programmer's Handbook for details. The MAX5580-MAX5585 include a 16-bit input shift register. The data is loaded into the input shift register through the serial interface. The 16 bits can be sent in two serial 8-bit packets or one 16-bit word (CS must remain low until all 16 bits are transferred). The data is loaded MSB first. For the MAX5580/MAX5581, the 16 bits consist of 4 control bits (C3-C0) and 12 data bits (D11-D0) (see Table 1). For the 10-bit MAX5582/ MAX5583 devices, D11-D2 are the data bits and D1 and D0 are sub-bits. For the 8-bit MAX5584/ MAX5585 devices, D11-D4 are the data bits and D3-D0 are sub-bits. Set all sub-bits to zero for optimum performance. Each DAC channel includes two registers: an input register and the DAC register. At power-up, the DAC output is set according to the state of PU. The DACs are double-buffered, which allows any of the following for each channel: * Loading the input register without updating the DAC register * Loading and updating the DAC register without updating the input register * Updating the DAC register from the input register * Updating the input and DAC registers simultaneously
Output Buffers
The DACA-DACD output-buffer amplifiers of the MAX5580-MAX5585 are unity-gain stable with Rail-toRail(R) output voltage swings and a typical slew rate of 3.6V/s (FAST mode). The MAX5580/MAX5582/ MAX5584 provide unity-gain outputs, while the MAX5581/MAX5583/MAX5585 provide force-sense outputs. For the MAX5581/MAX5583/MAX5585, access to the output amplifier's inverting input provides flexibility in output gain setting and signal conditioning (see the Applications Information section). The MAX5580-MAX5585 offer FAST and SLOW settlingtime modes. In the SLOW mode, the settling time is 6s (max), and the supply current is 1.6mA (max). In the FAST mode, the settling time is 3s (max), and the supply current is 4mA (max). See the Digital Interface section for settling-time mode programming details.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. 16
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Table 1. Serial Write Data Format
MSB CONTROL BITS C3 C2 C1 C0 D11 D10 D9 D8 D7
tCH SCLK tCL tDS DIN tCS0 tCSS CS tCSW tDO1 DOUTDC1* tDO2 DOUTDC0 OR DOUTRB* DOUT VALID DOUT VALID tCS1 C3 tDH C2 C1 D0 tCSH
MAX5580-MAX5585
16 BITS OF SERIAL DATA DATA BITS D6 D5 D4 D3 D2 D1
LSB D0
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
tCL SCLK tDS DIN tCS0 tDH tCCS CS tCSW tDS0 DSP tDSW DOUTDC0* tD01 DOUTDC1 OR DOUTRB* DOUT VALID tDSPWL tD02 tDSS tCS1 tCSH C3 C2 tCH C1 D0
DOUT VALID
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT). SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled) ______________________________________________________________________________________ 17
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all the serial-interface programming commands for the MAX5580-MAX5585. Table 2a shows the basic DAC programming commands, Table 2b gives the advanced-feature programming commands, and Table 2c provides the 24-bit read commands. Figures 3 and 4 provide serial-interface diagrams for write operations.
MICROWIRE VDD SK SO I/O VDD
Loading Input and DAC Registers
The MAX5580-MAX5585 contain a 16-bit shift register that is followed by a 12-bit input register and a 12-bit DAC register for each channel (see the Functional Diagrams). Tables 3, 4, and 5 highlight a few of the commands that handle the loading of the input and DAC registers. See Table 2a for all DAC programming commands.
SPI OR QSPI VDD
DVDD DSP SCLK DIN CS
MAX5580- MAX5585
VDD SCK MOSI SS OR I/O
DVDD DSP SCLK DIN CS
MAX5580- MAX5585
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. MICROWIRE and SPI Single DAC Writes (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1)
DSP VSS TCLK, SCLK, OR CLKX DT OR DX TFS OR FSX
SPI OR QSPI
MAX5580- DGND MAX5585
DSP SCLK DIN CS
MAX5580-
VSS SCK MOSI SS OR I/O DGND MAX5585 DSP SCLK DIN CS
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE: CS SCLK CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
COMMAND TAKES EFFECT HERE ONLY IF SCLK COUNT = N 16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. DSP and SPI Single DAC Writes (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) 18 ______________________________________________________________________________________
Table 2a. DAC Programming Commands
DATA BITS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION C0
DATA
CONTROL BITS
C3
C2
C1
INPUT REGISTERS (A-D) 0 D11 D10 D9 D8 D7 D6 D5 D4 Load DACA input register from shift register; D3/0 D2/0 D1/0 D0/0 DACA output register is unchanged; DACA output is unchanged.*
DIN
0
0
0
DIN
0
0
0
1
D11 D10
D9
D8
D7
D6
D5
D4
Load DACA output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACA output is updated.* D3/0 D2/0 D1/0 D0/0 Load DACA input register and output register from shift register; DACA output is updated.*
DIN
0
0
1
0
D11 D10
D9
D8
D7
D6
D5
D4
DIN
0
0
1
1
D11 D10
D9
D8
D7
D6
D5
D4
Load DACB input register from shift register; D3/0 D2/0 D1/0 D0/0 DACB output register is unchanged; DACB output is unchanged.*
DIN
0
1
0
0
D11 D10
D9
D8
D7
D6
D5
D4
Load DACB output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged. DACB output is updated.* D3/0 D2/0 D1/0 D0/0 Load DACB input register and output register from shift register; DACB output is updated.*
DIN
0
1
0
1
D11 D10
D9
D8
D7
D6
D5
D4
DIN
0
1
1
0
D11 D10
D9
D8
D7
D6
D5
D4
Load DACC input register from shift register; D3/0 D2/0 D1/0 D0/0 DACC output register is unchanged; DACC output is unchanged.*
DIN
0
1
1
1
D11 D10
D9
D8
D7
D6
D5
D4
Load DACC output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACC output is updated.* D3/0 D2/0 D1/0 D0/0 Load DACC input register and output register from shift register; DACC output is updated.* Load DACD input register from shift register; D3/0 D2/0 D1/0 D0/0 DACD output register is unchanged; DACD output is unchanged.*
DIN
1
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
DIN
1
0
0
1
D11 D10
D9
D8
D7
D6
D5
D4
MAX5580-MAX5585
______________________________________________________________________________________
0 D11 D10 D9 D8 D7 D6 D5 D4 Load DACD output register from shift register; D3/0 D2/0 D1/0 D0/0 input register is unchanged; DACD output is updated.*
DIN
1
0
1
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
19
MAX5580-MAX5585
DATA BITS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
20
C0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0 Load DACD input register and output register from shift register; DACD output is updated.* 0 D11 D10 D9 D8 D7 D6 D5 D4 Load all DAC input registers from the shift D3/0 D2/0 D1/0 D0/0 register; all DAC output registers are unchanged; all DAC outputs are unchanged.* D3/0 D2/0 D1/0 D0/0 1 D11 D10 D9 D8 D7 D6 D5 D4 DATA BITS C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C1 Function 1 0 0 0 X X X X X X MD MC MB MA Load DAC_ output register from input register when M_ is one; DAC_ output register is unchanged if M_ is zero. 1 1 X X X X X X 0 0 1 1 X X X X 0 0 1 0 X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 X X X X X Write DAC_ shutdownmode bits; see Table 8. Read DAC_ shutdownPDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 mode bits. 1 1 X X X X X X 0 1 0 1 X 0 1 0 0 X UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X Write UPIO configuration bits; see Table 18. X X X X X X X X Read UPIO configuration UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1 bits. 1 0 1 1 0 X X X X X SPDD SPDC SPDB SPDA Write DAC_ settling-timemode bits; see Table 11.
Table 2a. DAC Programming Commands (continued)
DATA
CONTROL BITS
C3
C2
C1
INPUT REGISTERS (A-D)
DIN
1
0
1
DIN
1
1
0
Load all DAC input and output registers from shift register; DAC outputs are updated.* *For the MAX5582/MAX5583 (10-bit version), D11-D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5584/MAX5585 (8-bit version), D11-D4 are the significant bits and D3-D0 are sub-bits. Set all sub-bits to zero during the write commands.
DIN
1
1
0
Table 2b. Advanced-Feature Programming Commands
DATA
CONTROL BITS
C3
C2
SELECT BITS
DIN
1
1
SHUTDOWN-MODE BITS
DIN
1
1
DIN
1
1
DOUTR
X
X
UPIO CONFIGURATION BITS
______________________________________________________________________________________
DIN
1
1
DIN
1
1
DOUTR
X
X
SETTLING-TIME-MODE BITS
DIN
1
1
Table 2b. Advanced-Feature Programming Commands (continued)
DATA BITS C0 0 X X X X X X X X X 1 1 1 X X X X X X X X X Read DAC_ settling-timeSPDD SPDC SPDB SPDA mode bits. D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function C1 1 X
DATA
CONTROL BITS
C3
C2
DIN DOUTR
1
1
X
X
DAC CPOL/CPHA BITS 1 1 X X X X X X X X X X X X 1 0 0 0 1 X X X X X X 1 0 0 0 0 X X X X X X CPOL CPHA Write CPOL, CPHA control bits.
DIN
1
1
DIN
1
1
DOUTR
X
X
X X Read CPOL, CPHA CPOL CPHA control bits.
UPIO_ AS GPI (GENERAL-PURPOSE INPUT) 1 1 0 0 1 X X X X X X X X X
DIN
1
1
DOUTRB
X
X
X
X
X
X
X
X
X
X
RTP2
LF2
LR2
RTP1
LF1
LR1
Read UPIO_ inputs (valid only when UPIO1 or UPIO2 is configured as a general-purpose input); see Table 21. Command is ignored.
OTHER COMMANDS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X X X X X 1 1 1 0 1 X X X X X X X X 1 1 1 1 0 0 X X X X X X X X X X 1 Command is ignored. Command is ignored. 16-bit no-op command. all DACs are unaffected.
DIN
1
1
DIN
1
1
DIN
1
1
DIN
1
1
MAX5580-MAX5585
______________________________________________________________________________________
X = Don't care.
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
21
MAX5580-MAX5585
DATA BITS FUNCTION
D9
D8
D7
D6
D5
D23
D22
D21
D20
D19
D18
D17
D16
D11
D10
D3/X
D2/X
D1/X
D15/X
D14/X
D13/X
D12/X
D0/X DAC register A (all 24 bits).** X Read input register B and DAC register B (all 24 bits).** X Read input D0/X D0/X D0/X register C and DAC register C (all 24 bits).** X Read input register D and DAC register D (all 24 bits).**
DOUTRB
X
X
X
X
X
X
X
X
DIN D9 D8 D7 D6 D5 D23 D22 D21 D20 D19 D18 D17 D16 D11 D10 D3/X D2/X D15/X D14/X D13/X D12/X D1/X X D1/X X D4 D3/X X D2/X X D1/X D6 D5 X 1 D9 D8 D7 D6 D5 D23 D22 D21 D20 D19 D18 D17 D16 D11 D10 D3/X D15/X D14/X D13/X E12/X D2/X X 1 D9 D8 D23 D22 D21 D20 D19 D18 D17 D16 D11 D15/X D14/X D13/X E12/X D10 X X X X D7 0 1 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X D4 0 0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X D4
1
1
1
1
0
1
1
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
D4
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
22
0 1 0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X Read input register A and X X X X
Table 2c. 24-Bit Read Commands
CONTROL BITS
DATA
C3 C2 C1 C0 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
READ INPUT AND DAC REGISTERS A--D
DIN
1
1
1
1
DOUTRB
X
X
X
X
DIN
1
1
1
1
DOUTRB
X
X
X
X
DIN
1
1
1
1
DOUTRB
X
X
X
X
X = Don't care.
**D23-D12 represent the 12-bit data from the appropriate DAC output register. D11-D0 represent the 12-bit data from the corresponding input register. For the MAX5582/MAX5583, bits D13, D12, D1, and D0 are don't-care bits. For the MAX5584/MAX5585, bits D15-D12 and D3-D0 are don't-care bits.
During readback, all ones (0xFF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out. CS must
______________________________________________________________________________________
be kept low while all 24 bits are clocked out.
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5580-MAX5585 can load all the input registers (A-D) simultaneously from the shift register, leaving the DAC registers unchanged (DAC output unchanged), by using the command in Table 4. To load all the input registers (A-D) and all the DAC registers (A-D) simultaneously, use the command in Table 5. For the 10-bit and 8-bit versions, set sub-bits = 0 for best performance.
Advanced-Feature Programming Commands
Select Bits (M_) The select bits allow synchronous updating of any combination of channels. The select bits command the loading of the DAC register from the input register of each channel. Set the select bit M_ = 1 to load the DAC register "_" with data from the input register "_", where "_" is replaced with A, B, C, or D, depending on the selected channel. Setting the select bit M_ = 0 results in no action for that channel (Table 6). Select Bits Programming Example: To load DAC register B from input register B while keeping other channels (A, C, D) unchanged, set MB = 1 and M_ = 0 (Table 7).
MAX5580-MAX5585
Table 3. Load Input Register A from Shift Register
DATA DIN 0 CONTROL BITS 0 0 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 4. Load Input Registers (A-D) from Shift Register
DATA DIN 1 CONTROL BITS 1 0 0 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 5. Load Input Registers (A-D) and DAC Registers (A-D) from Shift Register
DATA DIN 1 CONTROL BITS 1 0 1 D11 D10 D9 D8 D7 DATA BITS D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Table 6. Select Bits (M_)
DATA DIN 1 1 1 CONTROL BITS 0 0 0 X X X X X DATA BITS X MD MC MB MA
X = Don't care.
Table 7. Select Bits Programming Example
DATA DIN 1 1 1 CONTROL BITS 0 0 0 X X X X X DATA BITS X 0 0 1 0
X = Don't care.
______________________________________________________________________________________
23
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdownmode bits determine the output state of the selected channels. The shutdown-control bits put the selected channels into shutdown mode. To select the shutdown mode for DACA-DACD, set PD_0 and PD_1 according to Table 8 (where "_" is replaced with one of the selected channels (A-D)). The three possible states for unitygain versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with 100k output impedance. The three possible states for forcesense versions are 1) normal operation, 2) shutdown with 1k output impedance, and 3) shutdown with the output in a high-impedance state. Table 9 shows the commands for writing to the shutdown-mode bits. Table 10 shows an example of writing the shutdown-control bits. This command shuts down DACA with 1k to ground and shuts down DACB-DACD with 100k to ground. Always write the shutdown-mode-bits command first and then write the shutdown-control-bits command to properly shut down the selected channels. The shutdowncontrol-bits command can be written at any time after the shutdown-mode-bits command. It does not have to immediately follow the shutdown-mode-bits command. Settling-Time-Mode Bits (SPD_) The settling-time-mode bits select the settling time (FAST mode or SLOW mode) of the MAX5580-MAX5585. Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to select SLOW mode, where "_" is replaced by A, B, C, or D, depending on the selected channel (Table 11). FAST mode provides a 3s maximum settling time, and SLOW mode provides a 6s maximum settling time.
Table 8. Shutdown-Mode Bits
PD_1 0 PD_0 0 DESCRIPTION Shutdown with 1k termination to ground on DAC_ output. Shutdown with 100k termination to ground on DAC_ output for unity-gain versions. Shutdown with high-impedance output for force-sense versions. Ignored. DAC_ is powered up in its normal operating mode.
0
1
1 1
0 1
Table 9. Shutdown-Mode Write Command
DATA DIN 1 1 1 CONTROL BITS 0 0 1 0 X DATA BITS PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
X = Don't care.
Table 10. Shutdown-Mode-Bits Write Example
DATA DIN 1 1 1 CONTROL BITS 0 0 1 0 X 0 1 0 DATA BITS 1 0 1 0 0
X = Don't care.
Table 11. Settling-Time-Mode Write Command
DATA DIN 1 1 1 CONTROL BITS 0 1 1 0 X X X X DATA BITS X SPDD SPDC SPDB SPDA
X = Don't care.
24
______________________________________________________________________________________
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 12. To read back the settling-time-mode bits, use the command in Table 13. CPOL and CPHA Control Bits The CPOL and CPHA control bits of the MAX5580-MAX5585 are defined the same as the CPOL and CPHA bits in the SPI standard. Set the DAC's CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1 for MICROWIRE and SPI applications requiring the clocking of data in on the rising edge of SCLK. Set the DAC's CPOL and CPHA bits to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0 for DSP and SPI applications, requiring the clocking of data in on the falling edge of SCLK (refer to the Programmer's Handbook and see Table 14 for details). At power-up, if DSP = DVDD, the default value of CPHA is zero and if DSP = DGND, the default value of CPHA is one. The default value of CPOL is zero at power-up. To write to the CPOL and CPHA bits, use the command in Table 15. To read back the device's CPOL and CPHA bits, use the command in Table 16.
MAX5580-MAX5585
Table 12. Settling-Time-Mode Write Example
DATA DIN 1 1 1 CONTROL BITS 0 1 1 0 X X X X DATA BITS X 1 0 0 1
X = Don't care.
Table 13. Settling-Time-Mode Read Command
DATA DIN DOUTRB 1 X 1 X 1 X CONTROL BITS 0 X 1 X 1 X 1 X 1 X X X X X X X DATA BITS X X X X X X SPDD SPDC SPDB SPDA
X = Don't care.
Table 14. CPOL and CPHA Bits
CPOL 0 0 1 1 CPHA 0 1 0 1 DESCRIPTION Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge of SCLK. Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge of SCLK. Data is clocked in on the falling edge of SCLK. Data is clocked in on the rising edge of SCLK.
Table 15. CPOL and CPHA Write Command
DATA DIN 1 1 1 CONTROL BITS 1 0 0 0 0 X X X DATA BITS X X X CPOL CPHA
X = Don't care.
Table 16. CPOL and CPHA Read Command
DATA DIN DOUTRB 1 X 1 X 1 X CONTROL BITS 1 X 0 X 0 X 0 X 1 X X X X X X X DATA BITS X X X X X X X X CPOL CPHA
X = Don't care.
______________________________________________________________________________________
25
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
UPIO Bits (UPSL1, UPSL2, UP0-UP3) The MAX5580-MAX5585 provide two user-programmable input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 21. UPIO1 and UPIO2 can be programmed independently or simultaneously by writing to the UPSL1, UPSL2, and UP0-UP3 bits (Table 17). Table 18 shows how UPIO1 and UPIO2 are selected for configuration. The UP0-UP3 bits select the desired functions for UPIO1 and/or UPIO2 (Table 21). UPIO Programming Example: To set only UPIO1 as LDAC and leave UPIO2 unchanged, use the command in Table 19. The UPIO selection and configuration bits can be read back from the MAX5580-MAX5585 when UPIO1 or UPIO2 is configured as a DOUTRB output. Table 20 shows the read-back data format for the UPIO bits. Writing the command in Table 20 initiates a read operation of the UPIO bits. The data is clocked out starting on the 9th clock cycle of the sequence. Bits UP3-2 through UP0-2 provide the UP3-UP0 configuration bits for UPIO2 (Table 21), and bits UP3-1 through UP0-1 provide the UP3-UP0 configuration bits for UPIO1.
Table 17. UPIO Write Command
DATA DIN 1 1 1 CONTROL BITS 0 1 0 0 X UPSL2 UPSL1 UP3 DATA BITS UP2 UP1 UP0 X X
X = Don't care.
Table 18. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2 0 0 1 1 UPSL1 0 1 0 1 UPIO PORT SELECTED None selected UPIO1 selected UPIO2 selected Both UPIO1 and UPIO2 selected
Table 19. UPIO Programming Example
DATA DIN 1 1 1 CONTROL BITS 0 1 0 0 X 0 1 0 DATA BITS 0 0 0 X X
X = Don't care.
Table 20. UPIO Read Command
DATA DIN DOUTRB 1 X 1 X 1 X CONTROL BITS 0 X 1 X 0 X 1 X X X X X X DATA BITS X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don't care.
26
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
UPIO Configuration
Table 21 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3-UP0 configuration bits. Drive LDAC low to asynchronously load the DAC registers from their corresponding input registers (DACs that are in shutdown remain shut down). The LDAC input does not require any activity on CS, SCLK, or DIN to take effect. If LDAC is brought low coincident with a rising edge of CS (which executes a serial command modifying the value of either DAC input register), then LDAC must remain asserted for at least 120ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers. See Figures 5 and 6 for timing details.
MAX5580-MAX5585
LDAC LDAC controls the loading of the DAC registers. When LDAC is high, the DAC registers are latched, and any change in the input registers does not affect the contents of the DAC registers or the DAC outputs. When LDAC is low, the DAC registers are transparent, and the values stored in the input registers are fed directly to the DAC registers, and the DAC outputs are updated.
Table 21. UPIO Configuration Register Bits (UP3-UP0)
UPIO CONFIGURATION BITS UP3 0 0 0 0 0 0 UP2 0 0 0 0 1 1 UP1 0 0 1 1 0 0 UP0 0 1 0 1 0 1 FUNCTION LDAC SET MID CLR PDL Reserved DESCRIPTION Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers with data from input registers. Active-Low Input. Drive low to set all input and DAC registers to full scale. Active-Low Input. Drive low to set all input and DAC registers to midscale. Active-Low Input. Drive low to set all input and DAC registers to zero scale. Active-Low Power-Down Lockout Input. Drive low to disable software shutdown. This mode is reserved. Do not use. Active-Low 1k Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5580/MAX5582/MAX5584, drive SHDN1K low to pull OUTA-OUTD to AGND with 1k. For the MAX5581/MAX5583/MAX5585, drive SHDN1K low to leave OUTA-OUTD high impedance. Active-Low 100k Shutdown Input. Overrides PD_1 and PD_0 settings. For the MAX5580/MAX5582/MAX5584, drive SHDN100K low to pull OUTA-OUTD to AGND with 100k. For the MAX5581/MAX5583/MAX5585, drive low to leave OUTA-OUTD high impedance. Data Read-Back Output Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of SCLK. Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK. General-Purpose Logic Input General-Purpose Logic-Low Output General-Purpose Logic-High Output Toggle Input. Toggles DAC outputs between data in input registers and data in DAC registers. Drive low to set all DAC outputs to values stored in input registers. Drive high to set all DAC outputs to values stored in DAC registers. Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3s) mode or drive high to select SLOW (6s) settling mode. Overrides the SPDA-SPDD settings.
0
1
1
0
SHDN1K
0
1
1
1
SHDN100K
1 1 1 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
DOUTRB DOUTDC0 DOUTDC1 GPI GPOL GPOH TOGG
1
1
1
1
FAST
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27
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
tLDL LDAC END OF CYCLE* tGP
TOGG
PDL tCMS CLR, MID, OR SET tS VOUT_ PDL AFFECTS DAC OUTPUTS (VOUT_) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. 0.5 LSB
GPO_ LDAC tLDS
* END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
Figure 5. Asynchronous Signal Timing
Figure 6. GPO_ and LDAC Signal Timing
SET, MID, CLR The SET, MID, and CLR signals force the DAC outputs to full scale, midscale, or zero scale (Figure 5). These signals cannot be active at the same time. The active-low SET input forces the DAC outputs to full scale when SET is low. When SET is high, the DAC outputs follow the data in the DAC registers. The active-low MID input forces the DAC outputs to midscale when MID is low. When MID is high, the DAC outputs follow the data in the DAC registers.
The active-low CLR input forces the DAC outputs to zero scale when CLR is low. When CLR is high, the DAC outputs follow the data in the DAC registers. If CLR, MID, or SET signals go low during a write command, reload the data to ensure accurate results. Power-Down Lockout (PDL) The PDL active-low, software-shutdown lockout input overrides (not overwrites) the PD_0 and PD_1 shutdownmode bits. PDL cannot be active at the same time as SHDN1K or SHDN100K (see the Shutdown Mode (SHDN1K, SHDN100K) section). If the PD_0 and PD_1 bits command the DAC to shut down prior to PDL going low, the DAC returns to shutdown mode immediately after PDL goes high, unless the PD_0 and PD_1 bits were modified through the serial interface in the meantime.
SHDN1K low to select shutdown mode with OUTA- OUTD internally terminated with 1k to ground, or drive SHDN100K low to select shutdown with an internal 100k termination. For the MAX5581/MAX5583/ MAX5585, drive SHDN1K low for shutdown with 1k output termination, or drive SHDN100K low for shutdown with high-impedance outputs. Data Output (DOUTRB, DOUTDC0, DOUTDC1) UPIO1 and UPIO2 can be configured as serial data outputs, DOUTRB (data out for read back), DOUTDC0 (data out for daisy-chaining, mode 0), and DOUTDC1 (data out for daisy-chaining, mode 1). The differences between DOUTRB and DOUTDC0 (or DOUTDC1) are as follows: * The source of read-back data on DOUTRB is the DOUT register. Daisy-chain DOUTDC_ data comes directly from the shift register. Read-back data on DOUTRB is only present after a DAC read command. Daisy-chain data is present on DOUTDC_ for any DAC write after the first 16 bits are written. * The DOUTRB idle state (CS = high) for read back is high impedance. Daisy-chain DOUTDC_ idles high when inactive to avoid floating the data input in the next device in the daisy-chain. See Figures 1 and 2 for timing details. *
S Shutdown Mode (SHDN1K , SHDN100K) The SHDN1K and SHDN100K are active-low signals that override (not overwrite) the PD_1 and PD_0 bit settings. For the MAX5580/MAX5582/MAX5584, drive
28
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
GPI, GPOL, GPOH UPIO1 and UPIO2 can each be configured as a general-purpose input (GPI), a general-purpose output low (GPOL), or a general-purpose output high (GPOH). The GPI can serve to detect interrupts from Ps or microcontrollers. The GPI has three functions: 1) Sample the signal at GPI at the time of the read (RTP1 and RTP2). 2) Detect whether a falling edge has occurred since the last read or reset (LF1 and LF2). 3) Detect whether a rising edge has occurred since the last read or reset (LR1 and LR2). RTP1, LF1, and LR1 represent the data read from UPIO1; RTP2, LF2, and LR2 represent the data read from UPIO2. To issue a read command for the UPIO configured as GPI, use the command in Table 22. Once the command is issued, RTP1 and RTP2 provide the real-time status (0 or 1) of the inputs at UPIO1 or UPIO2, respectively, at the time of the read. If LF2 or LF1 is one, then a falling edge has occurred on the respective UPIO1 or UPIO2 input since the last read or reset. If LR2 or LR1 is one, then a rising edge has occurred since the last read or reset. GPOL outputs a constant low, and GPOH outputs a constant high. See Figure 6. TOGG Use the TOGG input to toggle the DAC outputs between the values in the input registers and DAC registers. A delay of greater than 100ns from the end of the previous write command is required before the TOGG signal can be correctly switched between the new value and the previously stored value. When TOGG = 0, the output follows the information in the input registers. When TOGG = 1, the output follows the information in the DAC register (Figure 5).
MAX5580-MAX5585
FAST The MAX5580-MAX5585 have two settling-time-mode options: FAST (3s max) and SLOW (6s max). To select the FAST mode, drive FAST low, and to select SLOW mode, drive FAST high. This overrides (not overwrites) the SPDA-SPDD bit settings.
Table 22. GPI Read Command
DATA DIN DOUTRB 1 X 1 X 1 X CONTROL BITS 1 X 0 X 0 X 1 X X X X X X X X RTP2 DATA BITS X LF2 X LR2 X RTP1 X LF1 X LR1
X = Don't care.
Table 23. Unipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (4095 / 4096) +VREF (2049 / 4096) +VREF (2048 / 4096) = VREF / 2 +VREF (2047 / 4096) +VREF (1 / 4096) 0
MAX5580
VOUT_ = VREF_ x CODE / 4096 WHERE CODE IS THE DAC INPUT CODE (0 TO 4095 DECIMAL)
MAX6126
REF
DAC_ OUT_
Figure 7. Unipolar Output Circuit
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29
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Applications Information
Unipolar Output
Figure 7 shows the unity-gain MAX5580 in a unipolar output configuration. Table 23 lists the unipolar output codes.
10k 10k
Bipolar Output
The MAX5580 outputs can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT_ = VREF x (CODE - 2048) / 2048 where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). Table 24 shows digital codes and the corresponding output voltage for the circuit in Figure 8.
MAX6126
DAC_ REF
V+
VOUT_
MAX5580 MAX5582 MAX5584
V-
Configurable Output Gain
The MAX5581/MAX5583/MAX5585 have force-sense outputs, which provide a direct connection to the inverting terminal of the output op amp, yielding the most flexibility. The force-sense output has the advantage that specific gains can be set externally for a given application. The gain error for the MAX5581/MAX5583/ MAX5585 is specified in a unity-gain configuration (opamp output and inverting terminals connected), and additional gain error results from external resistor tolerances. The force-sense DACs allow many useful circuits to be created with only a few simple external components. An example of a custom, fixed gain using the MAX5581's force-sense output is shown in Figure 9. In this example, the external reference is set to 1.25V, and the gain is set to +1.1V/V with external discrete resistors to provide an approximate 0 to 1.375V DAC output voltage range. VOUT = [(0.5 x VREF_ x CODE) / 4096] x [1 + (R2 / R1)] where CODE represents the numeric value of the DAC's binary input code (0 to 4095 decimal). In this example, R2 = 12k and R1 = 10k to set the gain = 1.1V/V: VOUT = [(0.5 x 1.25V x CODE) / 4096] x 2.2
Figure 9. Configurable Output Gain Figure 8. Bipolar Output Circuit
MAX6126
REF
DAC_ OUT_ R2 = 12k 0.1% 25ppm FB_ R1 = 10k 0.1% 25ppm
MAX5581
Table 24. Bipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (2047 / 2048) +VREF (1 / 2048) 0 -VREF (1 / 2048) -VREF (2047 / 2048) -VREF (2048 / 2048) = -VREF
30
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies by using a 10F capacitor in parallel with a 0.1F capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use shielding and/or ferrite beads to further increase isolation. Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use PC boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Using separate power supplies for AV DD and DVDD improves noise immunity. Connect AGND and DGND at the low-impedance power-supply sources (Figure 11).
MAX5580-MAX5585
AVDD 10F 0.1F 0.1F 10F
DVDD
ANALOG SUPPLY
AVDD MAX6126 1F** CS SCLK DIN PU DSP REF 0.1F** MAX5580- MAX5585 DVDD OUTA FBA* OUTB FBB* OUTC FBC* OUTD FBD* UPIO1 UPIO2 AGND*** DGND***
DIGITAL SUPPLY DVDD DGND
AVDD
AGND
10F
10F
0.1F
0.1F
AVDD
AGND
DVDD
DGND
DVDD
DGND
MAX5580-MAX5585
*MAX5581/MAX5583/MAX5585 ONLY. **REMOVE BYPASS CAPACITORS ON REF FOR AN AC REFERENCE INPUT. ***CONNECT ANALOG AND DIGITAL GROUND AT THE PLANES AT THE LOW-IMPEDANCE POWER-SUPPLY SOURCE.
DIGITAL CIRCUITRY
Figure 10. Bypassing Power Supplies AVDD, DVDD, and REF
Figure 11. Separate Analog and Digital Power Supplies
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31
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Pin Configurations
N.C. (*FBC) 17
TOP VIEW
AVDD REF AGND 1 AVDD 2 N.C. (*FBB) 3 OUTB 4 N.C. (*FBA) 5 OUTA 6 PU 7 CS 8 SCLK 9 **EP DIN 10 11 UPIO1 20 REF 19 N.C. (*FBC) 18 OUTC 17 N.C. (*FBD) N.C. (*FBB) OUTB N.C. (*FBA) OUTA PU 1 2 3 4 5 **EP 6 CS 7 SCLK 8 AGND
20
19
18
16 15 14 N.C. (*FBD)
MAX5580- MAX5585
16 OUTD 15 DSP 14 DGND 13 DVDD 12 UPIO2
OUTC
OUTD DSP
DGND DVDD
MAX5580- MAX5585
13 12 11
9
10 UPIO2
DIN
TSSOP *FOR THE MAX5581/MAX5583/MAX5585 **EXPOSED PADDLE CONNECTED TO AGND
THIN QFN
UPIO1
Ordering Information (continued)
PART MAX5580BEUP MAX5580BETP MAX5581AEUP* MAX5581AETP* MAX5581BEUP MAX5581BETP MAX5582EUP MAX5582ETP MAX5583EUP MAX5583ETP MAX5584EUP MAX5584ETP MAX5585EUP MAX5585ETP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP** 20 TSSOP-EP** 20 Thin QFN-EP**
Chip Information
TRANSISTOR COUNT: 24,393 PROCESS: BiCMOS
*Future product--contact factory for availability. Specifications are preliminary. **EP = Exposed paddle.
32
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Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX5580-MAX5585
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1
A3
PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
1
2
COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T2055-2 T2055-3 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 T4055-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20
NOM. MAX. ALLOWED
DOWN BONDS
3.00 3.00 3.00 3.00 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 0.30 0.40 0.50 40 10 10 -
NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES
3.30 3.40 3.20
3.30 3.40
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
2
2
______________________________________________________________________________________
33
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs MAX5580-MAX5585
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY EXPOSED PAD
21-0108
D
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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